Gate driving circuit for time division driving, method thereof and display apparatus having the same

A gate driving circuit comprising multiple shift register units connected in series, wherein it further comprises a shift delay module and a repeat output module, and the shift delay module is connected in series between the jth stage of shift register unit and the (j+1)th stage of shift register unit which are adjacent to each other wherein j is a positive integer;

• the shift delay module is connected to the output terminal of the jth stage of shift register unit and the input terminal of the (j+1)th stage of shift register unit, and also connected to the repeat output module;
• the repeat output module is connected to the output terminal of the (j−n+1)th stage of shift register unit and a clock control terminal, wherein n is a positive integer and n is equal to or less than j;
• and
• after the jth stage of shift register unit outputs a gate scan signal, a clock signal is input from the clock control terminal to turn on the repeat output module after a preset touch time ends, such that the shift delay module outputs a repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit through the repeat output module, and each of the shift register units from the (j−n+1)th stage to the jth stage re-outputs a scan signal to a gate line in sequence.