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US 9,519,330 B2Granted
Energy-efficient multicore processor architecture for parallel processing
AssigneeWisconsin Alumni Research Foundation
InventorNam-Sung Kim
Life of this patent
Estimating the term…
Abstract
A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.
Claims19
A computer system comprising:
- multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal;
- and
- a frequency selector associated with each given processor core having a selector input for receiving at least two non-zero frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
- wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core executing the at least one instruction;
- wherein the at least two frequency stable clock signals are received from at least one state machine divider without feedback stability requirements;
- wherein the at least one instruction of the instruction set is a synchronization instruction causing the frequency selector to select a reduced non-zero frequency-stable clock signal during a synchronization and causing the processor to spin while it waits for the synchronization to complete, to exit from the spin based on a event indicating synchronization is complete, and upon that exit causing the frequency selector to select an increased non-zero frequency-stable clock signal.
3 more elements
A computer system comprising:
- multiple processor core each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal;
- and
- a frequency selector associated with each given processor core haying a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
- wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core executing the at least one instruction:
- wherein the at least two frequency stable clock signals are received from at least one state machine divider without feedback stability requirements;
- wherein the at least one instruction provides a reduction in a processor core's execution capabilities that decreases core power consumption at a time before a change in selection input that decreases a frequency of the output clock to the processor core;
- the time before a change having a predetermined length to reduce electrical noise on a power distribution bus of the multiple processor cores.
4 more elements
A method of synchronizing multiple processor cores in a computer system having multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal:
- and
- a frequency selector associated with each given processor core having a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
- wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core's executing the at least one instruction;
- wherein the at least one instruction of the instruction set is a synchronization instruction causing the frequency selector to select a reduced non-zero frequency-stable clock signal during a synchronization and causing the processor to spin while it waits for the synchronization to complete, to exit from the spin based on a event indicating synchronization is complete, and upon that exit causing frequency selector to select an increased non-zero frequency-stable clock signal;
- the method comprising the steps of:
- (a) providing execution of a program among the multiple processor cores, the program having synchronization points;
- (b) in a given processor core, spinning at the synchronization points for a period of time in a synchronization process;
- (c) at a beginning of the period of time, decreasing the output clock to the given processor core;
- and
- (d) at an end of the period of time, increasing the output clock of the given processor core.
7 more elements
Dependencies are inferred from the claim text.