Power management controller, power management circuit using the same, and electronic device

A power management controller for controlling start and stop of a plurality of power supplies, each of which belongs to one of N rails, in which (N+1) states including a first state where all of the rails are turned off and a (k+1)th state (k=1, 2, . . . N) where a first rail to a kth rail are turned on are specified, the power management controller comprising:

• a task list memory configured to (i) store a first start instruction group to start up a power supply group included in the first rail in order, a second start instruction group to start up a power supply group included in the second rail in order, . . . , and an Nth start instruction group to start up a power supply group included in the Nth rail in order, and (ii) store an Nth stop instruction group to stop a power supply group included in the Nth rail in order, an (N−1)th stop instruction group to stop a power supply group included in the (N−1)th rail in order, . . . , a second stop instruction group to stop a power supply group included in the second rail in order, and a first stop instruction group to stop a power supply group included in the first rail in order, wherein, (iii) when the power management controller supports up-transition from an ith state to a jth state (j>i), for all supported j, an end instruction is inserted in an end of a (j−1)th start instruction group, (iv) when the power management controller supports down-transition from the jth state to the ith state (j>i), for all supported i, an end instruction is inserted in an end of an ith stop instruction group, (v) the end instruction included in the end of the ((j−1)th start instruction group is associated with a transition destination code, indicating that a transition destination is the jth state, and (vi) the end instruction included in the end of the ith stop instruction group is associated with a transition destination code, indicating that the transition destination is the ith state;
• a head address register file configured to (i) store a head address of the ith start instruction group for all supported i when the power management controller supports up-transition with the ith state as a starting point, and (ii) store a head address of the jth stop instruction group for all supported j when the power management controller supports down-transition with the jth state as a starting point;
• a state indicator indicative of a current state;
• an instruction execution unit configured to (i) read and execute, when a start address is designated, instruction groups stored in the task list memory in order with the designated start address as a starting point, (ii) stop the execution of the instruction groups upon reading an end instruction, and (iii) update data of the state indicator to a state indicated by a transition destination code associated with the end instruction upon reading the end instruction;
• and
• an event management unit configured to, (i) when the state indicator indicates the ith state, if a control signal satisfies an up-transition condition determined for the ith state, provide the head address of the ith start instruction group as a start address from the head address register file to the instruction execution unit, and (ii) when the state indicator indicates the jth state, if the control signal satisfies a down-transition condition determined for the jth state, provide the head address of the jth stop instruction group as a start address from the head address register file to the instruction execution unit.