Detecting full-system idle state in adaptive-tick kernels

A system comprising:

• plural CPUs, including a timekeeping CPU and one or more non-timekeeping CPUs;
• and
• one or more memory devices coupled to said CPUs, said memory devices including a computer readable storage medium tangibly embodying at least one program of instructions executable by said CPUs to implement an adaptive tick kernel, and operations for detecting full-system idle state in said adaptive-tick kernel, said operations comprising detecting a non-timekeeping CPU idle state, initiating a hysteresis period, waiting for said hysteresis period to end, manipulating a data structure whose state indicates whether a scheduling clock tick may be disabled on all of said CPUs, and disabling said scheduling clock tick on all of said CPUs if said data structure is determined to be in an appropriate state,
• wherein:
• said detecting a non-timekeeping CPU idle state comprises said timekeeping CPU detecting that all said non-timekeeping CPUs are in said idle state;
• said initiating a hysteresis period and said waiting for said hysteresis period to end use a global state variable that indicates whether or not all of said non-timekeeping CPUs are in an idle state, and if so, for how long;
• said global state variable being configured to store a first state indicating that at least one non-timekeeping CPU is in a non-idle state, a second state indicating that all of said non-timekeeping CPUs have been in an idle state for a relatively short time period, a third state indicating that all of said non-timekeeping CPUs have been in an idle state long enough that said global state variable may be changed without danger of excessive memory contention, a fourth state indicating that all of said non-timekeeping CPUs have been in an idle state long enough to warrant turning off said scheduling clock tick, and a fifth state indicating that said timekeeping CPU has noted said fourth state and turned off said scheduling clock tick on all of said CPUs;
• said initiating a hysteresis period comprises first and second hysteresis initiating operations;
• said waiting for said hysteresis period to end comprises first and second hysteresis period waiting operations;
• said first hysteresis initiating operation comprises said timekeeping CPU transitioning said global state variable from said first state to said second state, and performing a calculation to determine a first delay period for transition of said global state variable from said second state to said third state;
• said first hysteresis period waiting operation comprises said timekeeping CPU waiting until said first delay period has elapsed;
• said second hysteresis initiating operation comprises said timekeeping CPU transitioning said global state variable from said second state to said third second state, and performing a calculation to determine a second delay period for transition of said global state variable from said third state to said fourth state;
• said second hysteresis period waiting operation comprises said timekeeping CPU waiting until said second delay period has elapsed;
• said manipulating a data structure comprises said timekeeping CPU transitioning said global state variable from said third state to said fourth state after said second said delay period has elapsed;
• said disabling said scheduling clock tick on all of said CPUs is performed by said timekeeping CPU based on said global state variable being in said fourth state, and includes said timekeeping CPU transitioning said global state variable from said fourth state to said fifth state, then disabling the scheduling clock tick.

A computer program product comprising:

• one or more computer readable storage medium;
• and
• non-transitory program instructions provided by said one or more computer readable storage medium for programming a data processing platform to implement an adaptive tick kernel, and operations for detecting full-system idle state in said adaptive-tick kernel, said operations comprising detecting a non-timekeeping CPU idle state, initiating a hysteresis period, waiting for said hysteresis period to end, manipulating a data structure whose state indicates whether a scheduling clock tick may be disabled on all of said CPUs, and disabling said scheduling clock tick on all of said CPUs if said data structure is determined to be in an appropriate state,
• wherein:
• said detecting a non-timekeeping CPU idle state comprises said timekeeping CPU detecting that all said non-timekeeping CPUs are in said idle state;
• said initiating a hysteresis period and said waiting for said hysteresis period to end use a global state variable that indicates whether or not all of said non-timekeeping CPUs are in an idle state, and if so, for how long;
• said global state variable being configured to store a first state indicating that at least one non-timekeeping CPU is in a non-idle state, a second state indicating that all of said non-timekeeping CPUs have been in an idle state for a relatively short time period, a third state indicating that all of said non-timekeeping CPUs have been in an idle state long enough that said global state variable may be changed without danger of excessive memory contention, a fourth state indicating that all of said non-timekeeping CPUs have been in an idle state long enough to warrant turning off said scheduling clock tick, and a fifth state indicating that said timekeeping CPU has noted said fourth state and turned off said scheduling clock tick on all of said CPUs;
• said initiating a hysteresis period comprises first and second hysteresis initiating operations;
• said waiting for said hysteresis period to end comprises first and second hysteresis period waiting operations;
• said first hysteresis initiating operation comprises said timekeeping CPU transitioning said global state variable from said first state to said second state, and performing a calculation to determine a first delay period for transition of said global state variable from said second state to said third state;
• said first hysteresis period waiting operation comprises said timekeeping CPU waiting until said first delay period has elapsed;
• said second hysteresis initiating operation comprises said timekeeping CPU transitioning said global state variable from said second state to said third second state, and performing a calculation to determine a second delay period for transition of said global state variable from said third state to said fourth state;
• said second hysteresis period waiting operation comprises said timekeeping CPU waiting until said second delay period has elapsed;
• said manipulating a data structure comprises said timekeeping CPU transitioning said global state variable from said third state to said fourth state after said second said delay period has elapsed;
• said disabling said scheduling clock tick on all of said CPUs is performed by said timekeeping CPU based on said global state variable being in said fourth state, and includes said timekeeping CPU transitioning said global state variable from said fourth state to said fifth state, then disabling the scheduling clock tick.