Voltage contrast characterization structures and methods for within chip process variation characterization

An integrated circuit chip, comprising:

• a first region having only circuit features;
• a second region having only a passive voltage contrast characterization cell, said passive voltage contrast characterization cell having first features duplicating the size and relative positions of circuit features of a sub-region of said first region and having second features interconnected to form a ground feature;
• a third region having only fill shapes;
• said fill shapes not connected to each other or to any shape of said first or second regions;
• and
• wherein said first and second features of said second region are not connected to said circuit features of said first region or to said fill shapes of said third region.

A method comprising:

• providing an integrated circuit chip comprising:
• a first region having circuit features;
• a second region having a passive voltage contrast characterization cell, said passive voltage contrast having first features duplicating the size and relative positions of circuit features of a sub-region of said first region and having second features interconnected to form a ground feature;
• a third region having fill shapes;
• said fill shapes not connected to each other or to any shape of said first or second regions;
• and
• wherein said first and second features of said second region are not connected to said circuit features of said first region or to said fill shapes of said third region;
• placing said integrated circuit chip in a scanning electron microscope (SEM);
• and
• using said SEM, performing an inspection of said passive voltage contrast characterization cell under voltage contrast conditions.

A computer system comprising a processor, a memory coupled to the processor, and a computer readable storage device coupled to the processor, said storage device containing program code configured to be executed by the processor via the memory to implement a method for designing a voltage contrast characterization cell, said method comprising:

• (a) selecting a design level of a mask design shapes file stored on a non-transitory memory unit of the computer;
• (b) after (a) selecting a region of said design level having an open region having no fill shapes or design shapes and an adjacent circuit region having circuit design shapes;
• (c) after (b) selecting a sub-region of said circuit region adjacent to said open region;
• (d) after (c) using the computer, copying circuit design shapes of said sub-region to generate a characterization cell identical to the circuit design shapes of said sub-region;
• (e) after (d) modifying said characterization cell to generate a passive voltage contrast characterization cell;
• and
• (f) before placing fill shapes and after (e) placing said passive voltage contrast characterization cell into said open region adjacent to said sub-region to generate a modified design level and storing said modified design level on the memory unit of the computer.