Tap and aux circuitry with multiplexers on TDI, TDO, AUXI/O

An integrated circuit comprising:

• A. a serial instruction register having a serial data input coupled to a test data input, a serial data output, an instruction register control bus output, and a control bus input;
• B. a serial data register having a serial data input coupled to the test data input, a serial data output, and a control input coupled to the instruction register control bus output;
• C. first multiplexer circuitry coupling the serial data output of the instruction register and the serial data output of the data register to a test data output, and having a control input;
• D. TAP control circuitry having a test clock input, a test mode select input, and a TAP control bus output coupled to the control bus input of the instruction register and the control input of the first multiplexer circuitry;
• E. auxiliary circuitry coupled to the serial instruction register, the TAP control circuitry, the test data input, the test data output, and having a first control output, a first auxiliary input and a first auxiliary output;
• F. second multiplexer circuitry having a first input coupled with the test data input, a second input, and an output coupled with the serial data input of the serial instruction register and the serial data register;
• G. an input buffer having an input coupled to an auxiliary input and output lead and an output coupled with the first auxiliary input and the second input of the second multiplexer circuitry;
• H. a tristate output buffer having an input coupled with the first auxiliary output, an output coupled with the auxiliary input and output lead, and a control input;
• and
• I. third multiplexer circuitry having a first input coupled with the first control output, a second input having a fixed logic state, and an output coupled with the control input of the tristate output buffer.