Method and apparatus for driving half bridge connected semiconductor power switches with a stable and extremely short interlock delay combined with a switching transition speed increase and a driving power consumption reduction

A driving circuit for driving half bridge connected electrically controlled power switches with a near zero interlock delay time between on-states of the power switches,

• wherein the driving circuit is configured to receive an input signal and to generate:
• a first drive signal, wherein said first drive signal controls a first power switch and is adapted to switch between an on-voltage and an off-voltage,
• a second drive signal, wherein said second drive signal controls a second power switch and is adapted to switch between said on-voltage and said off-voltage,
• wherein said on-voltage is deep in an ohmic region of said first power switch and said second power switch;
• wherein said off-voltage is deep in a cutoff region of said first power switch and said second power switch;
• wherein transition of said first drive signal and transition of said second drive signal start simultaneously with rising and falling edges of said input signal;
• wherein a signal curve of said transition of said first drive signal and a signal curve of said transition of said second drive signal have complementary slopes;
• wherein the signal curve of said first drive signal is mirrored with respect to said signal curve of said second drive signal along a mirroring voltage value level at least within a transition time;
• and
• wherein the mirroring voltage value is adjusted to be within the cutoff region of the power switches.

A method for driving half bridge connected electrically controlled power switches in terms of having a near zero interlock delay time between on-states of the power switches comprising the steps of:

• generating a first and a second triggering signal,
• wherein the first triggering signal changes as a response to every odd step change of an input signal its value in a step manner from an off-voltage state to a positive DC gate supply voltage simultaneously with the second triggering signal which changes its value in a step manner from an on-voltage state to a negative DC gate supply voltage end
• wherein the first triggering signal changes as a response to every even step change of an input signal its value in a step manner from an on-voltage state to a negative DC gate supply voltage simultaneously with the second triggering signal which changes its value in a step manner from an off-voltage state to a positive DC gate supply voltage,
• sloping said first and said second triggering signal to a first and a second drive signal with equal slopes as a response to the rising and falling edges of the input signal,
• wherein said first and second drive signal are adapted to switch a corresponding power switch among the on and off state,
• wherein said first and second drive signal are mirrored with respect to one another's time curve along the time axis through a mirroring voltage value within a transition time and
• wherein the said mirroring voltage value is adjusted to be low enough for said power switches to be within a cutoff region.