US 9,466,363 B2 · Integrated circuit

Abstract

An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0<λ1≦1).

Claims26

Dependent claims

An integrated circuit, comprising:

a memory element where write into the memory element occurs when specified period τ has elapsed after a write signal is input to the integrated circuit;
and
a basic circuit including elementary devices that constitute a circuit, the basic circuit having a data retaining function, wherein an operation frequency f1 in a first operation mode of memory access of the basic circuit satisfies the following relation:
τ>λ1/f1(0<λ1≦1)
wherein λ1 represents the ratio of time when write into the basic circuit is being performed in a cycle of the first operation mode (1/f1) of memory access of the basic circuit.

2 more elements

Dependencies are inferred from the claim text.

Integrated circuit

Life of this patent

Integrated circuit

Life of this patent

Abstract

Claims26