Fractional-N all digital phase locked loop incorporating look ahead time to digital converter

A look-ahead time to digital converter (TDC) for use in an all digital phase locked loop (ADPLL) circuit, comprising:

• a look-ahead circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and to generate a delayed frequency reference clock therefrom aligned with a variable clock (CKV);
• a plurality of controllable delay elements coupled to said look-ahead circuit, said plurality of delay elements configured in a sequential chain configuration, said delay element chain operative to receive the delayed frequency reference clock and to propagate a single disturbance pulse through a number of delay elements that function as a time to digital converter (TDC);
• wherein said plurality of controllable delay elements are operative to generate an output code representing a fractional portion of a phase error used by said ADPLL to adjust the frequency of the variable clock;
• and
• wherein one or more delay elements perform a look-ahead function acting as a digital to time converter (DTC) and one or more other delay elements perform a sampling function for resolving a delayed frequency reference clock to variable clock (CKV) time delay.

A method of look-ahead time to digital conversion for use in an all digital phase locked loop (ADPLL), the method comprising:

• predicting reference frequency (FREF) clock edge timing and generating a delayed frequency reference clock therefrom;
• providing a plurality of controllable delay elements configured in a sequential chain configuration;
• and
• based on the reference frequency clock prediction, selecting at every frequency reference clock a number of delay elements in said chain to function as a digital to time converter and a portion of a remainder of delay elements in said chain to function as a time to digital converter.