Video multiviewer system using direct memory access (DMA) registers and block RAM

A video multiviewer system comprising:

• a graphics processing unit (GPU) comprising a GPU memory;
• a Direct Memory Access (DMA) controller;
• a Read/Write controller;
• a video input module configured to receive simultaneously a plurality of video streams corresponding to video data and transfer the video data to the GPU memory via DMA, wherein the video input module comprises a Field Programmable Gate Array (FPGA) comprising a dual ported Block Random Access Memory (RAM) comprising Pre-read registers, Write Back registers and Working registers, and further comprising first and second ports, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the DMA controller and the Read/Write controller are operative together with the Pre-read registers, Write Back registers and Working registers for receiving the video data and allowing uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels through the first port, and the second port is configured to access the video data of the plurality of DMA channels using simultaneous read/write access by the DMA controller through the second port;
• and
• a display configured to receive the video data stored at the GPU memory and simultaneously present video streams in respective windows of the display.

A method for displaying multiple video windows on a video multiviewer display, comprising:

• receiving, at a video input module, simultaneously a plurality of video streams corresponding to video data, wherein the video input module is coupled to a Graphics Processing Unit (GPU) having a GPU memory and further coupled to a DMA controller;
• transferring the video data to the GPU memory via DMA through a programmable circuit having a dual ported Block Random Access Memory (RAM) comprising first and second ports, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module and is further configured to allow uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels through the first port, and the second port is configured to access video data in the plurality of DMA channels using simultaneous read/write access by the DMA controller through the second port;
• receiving, at a display, the video data stored at the GPU memory;
• and
• presenting simultaneously video streams in respective windows.