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US 9,438,539 B1Granted
Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches
AssigneeXpliant, Inc.
InventorsTsahi Daniel, Enric Musoll, Sridevi Polasanapalli
Life of this patent
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Abstract
A packet processor includes a packet memory manager configured to receive a single header reference count and a single payload reference count for a packet. A page link list walk for the header under the control of the header reference count is performed in parallel with a page link list walk for the payload under the control of the payload reference count.
Claims7
A packet processor, comprising:
- a packet memory manager configured to
- receive a single header reference count and a single payload reference count for a packet with a header and a payload;
- and
- perform in parallel a page link list walk for the header under the control of the single header reference count and a page link list walk for the payload under the control of the single payload reference count, wherein each page link list walk traverses a linked list of all pages that a particular packet uses in packet memory.
1 more element
Dependencies are inferred from the claim text.