Centering baud-rate CDR sampling phase in a receiver

A receiver, comprising:

• a front end operable to receive from a transmitted signal from a channel;
• a data slicer operable to generate data samples from output of the front end;
• an error slicer operable to generate error samples from the output of the front end;
• a clock data recovery (CDR) circuit operable to generate a common sampling clock phase for both the data slicer and the error slicer from output of the data samples and the error samples;
• and
• a decision adapt circuit operable to set a decision threshold of the error slicer, wherein for each main-cursor data sample of the data samples the decision adapt circuit is operable to adjust the decision threshold based on a sum of at least one term, each of the at least one term being a product of a scalar and one of a pre-cursor data sample or a post-cursor data sample.

A method of clock data recovery (CDR) for a receiver, comprising:

• generating, at a baud-rate, data samples derived from a received signal using a data slicer;
• generating, at a baud-rate, error samples derived from the received signal using an error slicer;
• generating a common sampling clock phase for both the data slicer and the error slicer from the data samples and the error samples;
• and
• setting a decision threshold of the error slicer for each main-cursor data sample of the data samples by adjusting the decision threshold based on a sum of at least one term, each of the at least one term being a product of a scalar and one of a pre-cursor data sample or a post-cursor data sample.