LLR computation device and error correction decoding device
AssigneeMitsubishi Electric Corporation
InventorsKenya Sugihara, Wataru Matsumoto
Life of this patent
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Abstract
A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.
Claims20
A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising:
- a reference-point-pair determination circuitry that determines first/second reference point pairs by selecting two transmission symbol points each of whose k-th bit is 0 and two transmission symbol points each of whose k-th bit is 1, each of the first/second reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1;
- and
- an LLR computation unit circuitry that calculates an LLR for a received signal point by
- calculating a first LLR based on the first reference point pair and the received signal point and also calculating a second LLR based on the second reference point pair and the received signal point,
- assigning weights to the first/second LLRs and adding up the weighted first/second LLRs, and
- adding, to a result of the addition of the weighted first/second LLRs, a correction term.
A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising:
- a reference-point-pair determination circuitry that determines first/second reference point pairs by selecting two transmission symbol points each of whose k-th bit is 0 and two transmission symbol points each of whose k-th bit is 1, each of the first/second reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1;
- a square difference calculation circuitry that calculates a difference between squared distances from a received signal point to each of the two transmission symbol points whose k-th bit is 0 and also calculate a difference between squared distances from the received signal point to each of the two transmission symbol points whose k-th bit is 1;
- and
- an LLR computation circuitry that calculates an LLR for the received signal point by a prescribed LLR computation expression using the differences calculated by the square difference calculation circuitry.
A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising:
- a reference-point-pair determination circuitry that determines first/second/third reference point pairs by selecting three transmission symbol points each of whose k-th bit is 0 and three transmission symbol points each of whose k-th bit is 1, each of the first/second/third reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1;
- and
- an LLR computation circuitry that calculates an LLR for a received signal point by
- calculating a first LLR based on the first reference point pair and the received signal point, calculating a second LLR based on the second reference point pair and the received signal point, and also calculating a third LLR based on the third reference point pair and the received signal point,
- assigning weights to the first/second/third LLRs and adding up the weighted first/second/third LLRs, and
- adding, to a result of the addition of the weighted first/second/third LLRs, a correction term.
A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising:
- a reference-point-pair determination circuitry that determines four or more reference point pairs by selecting four or more transmission symbol points each of whose k-th bit is 0 and four or more transmission symbol points each of whose k-th bit is 1, each of the reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1;
- and
- an LLR computation circuitry that calculates an LLR for a received signal point by
- calculating four or more LLRs based on the individual reference point pairs and the received signal point,
- assigning weights to the four or more LLRs and adding up the weighted LLRs, and
- adding, to a result of the addition of the weighted LLRs, a correction term.
Dependencies are inferred from the claim text.