Digital phase locked loop circuitry and methods

A method for converting parallel data to serial data, the method comprising:

• receiving, at a first clock rate, the parallel data;
• generating, at a second clock rate, a first set of serial data comprising each bit of the parallel data arranged one bit after another in succession;
• and
• replicating each bit of the first set of serial data onto a number of parallel leads, wherein the number is based on a ratio of the first clock rate and the second clock rate.

Apparatus for converting parallel data to serial data, the apparatus comprising:

• serializer circuitry for:
• receiving, at a first clock rate, a first set of parallel data;
• and
• generating, at a second clock rate, a first set of serial data comprising each bit of the first set of parallel data arranged one bit after another in succession;
• and
• circuitry for generating a second set of parallel data comprising a number of instances, arranged in parallel, of each successive bit of the first set of serial data, wherein the number is based on a ratio of the first clock rate and the second clock rate.