US 9,438,266 B1Granted

Calibrated-output analog-to-digital converter apparatus and methods

AssigneeTexas Instruments Incorporated

InventorsKrishnaswamy Nagaraj, Manish Goel, Xiao Pu, Hun-Seok Kim

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Abstract

A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

Claims20

Dependent claims

A calibrated-output analog-to-digital converter (“ADC”), comprising:

a multi-level sigma-delta modulator including an N-level current-mode digital-to-analog converter (“I-DAC”) coupled to at least one output terminal of the modulator to provide a negative feedback loop in the modulator, the I-DAC implemented with (N−1)/2 switched current sources;
mismatch measurement logic coupled between a modulator input terminal and the modulator output terminals to determine, from counts of occurrences of modulator output levels during (N−1)/2 mismatch measurement intervals, magnitudes of [(N−1)/2−1] mismatch errors (“δ1”, “δ2” . . . “δ_[(N−1)/2−1]”) (collectively, “delta”), each mismatch error corresponding to a difference in amplitude of currents from each of a set of two of the (N−1)/2 switched current sources transposed prior to each mismatch measurement interval following a first mismatch measurement interval;
and
a mismatch-correcting split decimator coupled to the modulator output terminals to apply a decimation filtering to output data from the sigma-delta modulator in order to generate an uncorrected ADC output data component, to multiply decimated counts of modulator output levels predetermined to be delta-influenced by a predetermined factor of at least one of δ1, δ2 . . . δ_[(N−1)/2−1] in order to generate at least one ADC output error component, and to sum the ADC output error components with the uncorrected ADC output data component to generate a calibrated ADC output data component corrected for δ1, δ2 . . . δ_[(N−1)/2−1].

1 more element

A method of generating calibrated output data from an N-level sigma-delta analog-to-digital converter (“ADC”), comprising:

during a series of mismatch measurement intervals, counting occurrences of voltage levels at output terminals of a sigma-delta modulator portion of the ADC associated with each of (N−1)/2 configurations of an N-level current mode digital-to-analog converter (“I-DAC”) negative feedback element associated with the modulator;
determining an amplitude mismatch (“delta”) between at least one pair of [(N−1)/2−(1)] current sources in the I-DAC from the counts of occurrences of the modulator output voltage levels;
during normal operation of the ADC, applying a decimation filtering to output data from the modulator to generate an uncorrected ADC output data component;
multiplying decimated modulator output levels predetermined to be delta-influenced by a predetermined factor of delta in order to generate at least one ADC output data error component;
and
summing the ADC output data error components with the uncorrected ADC output data component to generate calibrated ADC output data corrected for delta.

3 more elements

A method of determining mismatch errors in an N-level sigma-delta analog-to-digital converter (“ADC”), comprising:

applying a reference voltage (“V_CAL”) to an input terminal of the ADC during (N−1)/2 mismatch measurement intervals;
in an N-level current mode digital-to-analog converter (“I-DAC”) negative feedback element associated with a sigma-delta modulator portion of the ADC, establishing an operational assignment of each of (N−1)/2 switched current sources to one of (N−1)/2 level selection switch matrices, the operational assignment to determine a contribution of each current from each switched current source to each of N modulator output levels;
at output terminals of the modulator, counting a number of occurrences of each modulator output level at sampling times during a first mismatch measurement interval in order to generate a first set of counts {A}=A1, A2 . . . A_N;
transposing each of [(N−1)/2−(1)] pairs of the switched current sources relative to the operational assignment;
at the modulator output terminals, counting a number of occurrences of each modulator output level during a subsequent mismatch measurement interval following each transposition of one of the pairs of switched current sources in order to generate subsequent sets of counts {B}=B1, B2 . . . B_N, {C}=C1, C2 . . . C_N . . . {Z}=Z1, Z2 . . . Z_N, modulator output data errors resulting from amplitude mismatches δ1, δ2 . . . δ_[(N−1)/2−(1)] between transposed current sources appearing in counts associated with predetermined modulator output levels during each mismatch measurement interval;
and
calculating each of δ1, δ2 . . . δ_[(N−1)/2−(1)] as an algebraic function of A1, A2 . . . A_N, B1, B2 . . . B_N, C1, C2 . . . C_N . . . Z1, Z2 . . . Z_N, each algebraic function resulting from V_CAL being equal to an average of each set of counts after each count is weighted by an amount equal to the level corresponding to the count (V_CAL=AVG_{A_WEIGHTED}(δ)=AVG_{B_WEIGHTED}(δ) . . . =AVG_{Z_WEIGHTED}(δ)).

4 more elements

Dependencies are inferred from the claim text.