Semiconductor apparatus and calibration method for analog to digital converter

A method of calibrating an analog to digital converter including a sub ADC that outputs a digital intermediate value corresponding to a signal level of an input signal as a multi-bit digital value, a sub DAC that outputs an analog intermediate value corresponding to the digital intermediate value, a residue amplifier that amplifies a difference between the input signal and the analog intermediate value and outputs a residue signal, and an output stage circuit that outputs a digital output value generated by correcting the digital intermediate value by a correction coefficient, the method comprising:

• switching combinations of a plurality of unit elements and bits of a digital intermediate value used by the unit elements to generate an analog value, the plurality of unit elements being provided to correspond to a total number of weights for each bit of the digital intermediate value in the sub DAC, and the same capacitance, the same resistance value, or the same current value being set to the plurality of unit elements;
• performing an analog to digital conversion process on each of the combinations of the unit elements and the bits, the analog to digital conversion process using a most significant digital intermediate value corresponding to a most significant bit of a conversion result in the digital intermediate value being fixed to a previously determined value;
• and
• obtaining the digital intermediate value for each of the combinations of the unit elements and the bits and calculating the correction coefficient according to the obtained digital intermediate value.