Slow to fast clock synchronization

A method, comprising:

• receiving data from circuits included in a first clock domain;
• sampling the data dependent upon a clock signal included in the first clock domain to generate sampled data;
• synchronizing the clock signal included in the first clock domain to generate a synchronized clock signal, wherein at least one transition of the synchronized clock signal corresponds to a transition of a clock signal included in a second clock domain;
• wherein a frequency of the clock signal included in the first clock domain is lower than a frequency of the clock signal included in the second clock domain;
• detecting an edge of the synchronized clock signal included in the first clock domain;
• asserting an enable signal responsive to the detection of the edge of the synchronized clock signal;
• and
• capturing, in response to the assertion of the enable signal, the sampled data dependent upon the clock signal included in the second clock domain;
• wherein synchronizing the clock signal included in the first clock domain includes:
• sampling, using a first flip-flop circuit, the clock signal included in the first clock domain dependent upon the clock signal included in the second clock domain;
• and
• sampling, using a second flip-flop circuit, an output of the first flip-flop circuit dependent upon the clock signal included in the second clock domain.

A system, comprising:

• a first circuit block using a first clock signal;
• and
• a second circuit block coupled the first circuit block and using a second clock signal, wherein the a frequency of the first block signal is lower than a frequency of the second clock signal, and wherein the second circuit block includes a synchronization unit configured to:
• sample data received from the first circuit block dependent upon a the first clock signal to generate sampled data;
• generate a synchronized first clock signal dependent upon the second clock signal, wherein at least one transition of the synchronized first clock signal corresponds to a transition of the second clock signal;
• detect an edge of the synchronized first clock signal;
• and
• assert an enable signal in response to the detection of the edge of the synchronized first clock signal;
• and
• capture, in response to the assertion of the enable signal, the sampled data dependent upon the second clock signal;
• wherein to generate the synchronized first clock signal, the synchronization unit is further configured to:
• sample the first clock dependent upon the second clock signal to generate a sampled first clock;
• and
• capture the sampled first clock dependent upon the second clock signal.