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US 9,438,255 B1Granted
High frequency delay lock loop systems
AssigneeInphi Corporation
InventorsGuojun Ren, James Gorecki, Karthik S. Gopalakrishnan
Life of this patent
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Abstract
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
Claims20
A delay-lock loop (DLL) system comprising:
- a receiver interface for receiving a square clock signal, a first bias voltage and a second bias voltage;
- an input conditioning module configured to maintain an edge shape of the clock signal;
- a delay line comprising m delay modules arranged in series configured to generate n delayed signals;
- an output driver coupled to the delay line and configured to generate n output signals, the n output signals including a first signal pair and a second signal pair, the first signal pair including a first phase signal and a last phase signal, the second signal pair being associated a second phase signal and a third phase signal, the second phase signal having an adjacent phase relative to the third phase signal;
- a phase detector being configured to generate correction signal by at least comparing the first signal pair and the second signal pair;
- a capacitor configured to for integrating the correction signal;
- and
- a bias voltage module configure to generate the first bias voltage and the second bias voltage using at least the correction signal.
5 more elements
A receiver system comprising:
- a PLL module configured to provide a reference clock signal;
- a phase interpolator configured to generate a corrected clock signal based reference clock signal;
- and
- a delay lock loop (DLL) device comprising:
- a delay line comprising m delay modules arranged in series configured to generate n delayed signals based on a corrected clock signal and a pair of bias voltages, the pair of bias voltages including a first voltage and a second voltage;
- an output driver coupled to the delay line and configured to generate n output signals, the n output signals including a first signal pair and a second signal pair, the first signal pair including a first phase signal and a last phase signal, the second signal pair being associated a second phase signal and a third phase signal, the second phase signal having an adjacent phase relative to the third phase signal;
- a phase detector being configured to generate correction signal by at least comparing the first signal pair and the second signal pair, the phase detector comprising an OTA for comparing the first signal pair and the second signal pair;
- a capacitor configured to for integrating the correction signal;
- and
- a bias voltage module configure to generate the first bias voltage and the second bias voltage using at least the correction signal.
7 more elements
A delay-lock loop (DLL) system comprising:
- a delay line comprising m delay modules arranged in series configured to generate n delayed signals based on a reference clock signal and a pair of bias voltages, the pair of bias voltages including a first voltage and a second voltage;
- an output driver coupled to the delay line and configured to generate n output signals, the n output signals including a first signal pair and a second signal pair, the first signal pair including a first phase signal and a last phase signal, the second signal pair being associated a second phase signal and a third phase signal, the second phase signal having an adjacent phase relative to the third phase signal;
- a phase detector being configured to generate correction signal by at least comparing the first signal pair and the second signal pair, the phase detector comprising a OTA for comparing the first signal pair and the second signal pair, the phase detector comprising a first AND gate for generating a first compare signal based on the first signal pair;
- and
- a bias voltage module configure to generate the first bias voltage and the second bias voltage using at least the correction signal.
2 more elements
Dependencies are inferred from the claim text.