High speed current mode latch
AssigneeTexas Instruments Incorporated
InventorMustafa Ulvi Erdogan
Life of this patent
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Abstract
A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.
Claims20
A current mode logic (CML) latch, comprising:
- a first transistor coupled to a second transistor, the first and second transistors configured to receive a data signal;
- a third transistor coupled to a fourth transistor, the third and fourth transistors configured to receive a clock signal,
- a first capacitor connected to the first, second, third, and fourth transistors;
- and
- a second capacitor connected to the third and fourth transistors, the first and second capacitors being cross-coupled with the third and fourth transistors such that parasitic capacitance in the CML latch is offset.
A clock and data recovery (CDR) circuit, comprising:
- a phase-frequency detector (PFD) circuit including a current mode logic (CML) latch that comprises a first and a second transistor configured to receive a data signal, and a first and a second capacitor cross-coupled to a third and a fourth transistor, the third and fourth transistors configured to receive a clock signal;
- and
- a voltage-controlled oscillator (VCO) coupled to the PFD, the VCO configured to generate a VCO output signal.
A communication system, comprising:
- a transmitter;
- a clock and data recovery (CDR) circuit coupled to the transmitter, the CDR circuit configured to receive a data signal from the transmitter, generate a clock signal from the data signal, and generate an output signal;
- and
- a receiver coupled to the CDR circuit, the receiver configured to receive the output signal,
- wherein the CDR circuit includes a current mode logic (CML) latch that includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor, the first capacitor is connected to a gate of the third transistor and a drain of the fourth transistor and the second capacitor is connected to a gate of the fourth transistor and a drain of the third transistor.
Dependencies are inferred from the claim text.