Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same

A programmable delay generator, comprising:

• a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit;
• and
• a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit;
• wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO;
• and
• wherein the frequency comparator is configured to generate a varying multi-bit digital calibration code during a calibration operation and store a final digital calibration code upon completion of the calibration operation.

A programmable delay generator, comprising:

• a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit;
• and
• a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit;
• wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO;
• and
• wherein said calibration circuit comprises a feedback divider configured to generate the periodic feedback signal in response to the periodic signal generated by said DCO during a calibration operation;
• and wherein said DCO and the feedback divider are disabled into a low power state upon completion of the calibration operation.

A programmable delay generator, comprising:

• a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit;
• and
• a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit;
• wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive a digital calibration code and a current-to-voltage converter responsive to at least one current signal generated by said CSDAC;
• and
• wherein said calibration circuit further comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO, said frequency comparator configured to generate the digital calibration code as a varying code during a calibration operation and store a final digital calibration code upon completion of the calibration operation.