US 9,438,251 B2Granted

Clock generating circuit, semiconductor device including the same, and data processing system

AssigneePS4 Luxco S.a.r.l.

InventorKazutaka Miyano

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Abstract

A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock signal, adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal, switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, and the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal.

Claims16

Dependent claims

A method for generating an internal clock signal by a clock generating circuit, comprising:

generating the internal clock signal based on an external clock signal;
adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal;
and
switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value,
wherein the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal, and
the switching includes switching from the first operation mode to the second operation mode in response to a state where the internal clock signal attains a predetermined phase;
wherein the trigger signal is generated in response to an output signal of a power detecting circuit, and wherein the power detecting circuit outputs a first level of the output signal when a power supply voltage varies equal to or higher than a reference acceleration and outputs a second level of the output signal when the power supply voltage varies smaller than the reference acceleration, the first and second levels being different from each other.

4 more elements

A method for generating a clock by a clock generating circuit comprising:

receiving a first clock signal and a first control signal and outputting a second clock signal;
comparing the second clock signal with the first clock signal and outputting a comparison signal;
and
receiving the comparison signal and sending the first control signal to control the outputting the second clock signal,
wherein the clock generating circuit is controlled by a control circuit outputting a second control signal, the second control signal being output in response to at least a first detection signal that is generated when a first variation of a power supply voltage has been detected;
and
the detection signal is generated by a detecting circuit, the detecting circuit including:
first, second and third resistor circuits each coupled between a power supply and a ground;
a first comparator including a first input node coupled to the first resistor circuit and a second input node coupled to the third resistor circuit, and including an output node;
a second comparator including a first input node coupled to the third resistor circuit and the second resistor circuit, and including an output node;
and
an AND gate including a first input node coupled to the output node of the first comparator and the second input node coupled to the output node of the second comparator, and the AND gate outputting an output signal of the detecting circuit.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/679,450Filed 6 Apr 2015 · continuation
Priority: JP 2009-2084559 Sep 2009
Published: US 2015/0214962 A130 Jul 2015
Granted: 6 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H03L 7/0818
And where no voltage or current controlled oscillator is used: the controlled phase shifter comprising coarse and fine delay or phase-shifting means
G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…

Family

Application12/805,652Parent of this continuation · filed 11 Aug 2010
US 2015/0214962 A1Pre-grant publication · published 30 Jul 2015
US 9,007,861 B2Parent of this continuation
US 2011/0058437 A1Published application
US 9,438,251 B2This patent

From the US filing history. Foreign family members aren’t listed.

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