Systems and methods for reducing power consumption in semiconductor devices

An integrated circuit, comprising:

• a first circuit having a first logic circuit coupled to a first cell of a first design to establish a first timing path, wherein the first cell has a first transistor spaced from a boundary of a first well;
• a second circuit having a second logic circuit coupled to a second cell of the first design;
• wherein
• the second cell is slower than the first cell;
• the second cell has a second well analogous to the first well;
• the second well has a boundary analogous in location to the boundary of the first well;
• and
• the second cell is closer to the boundary of the second well than the first cell is to the boundary of the first well.

A method of making a first timing path, comprising:

• analyzing a first design for the first timing path to determine if the first design results in positive timing slack;
• and
• if the first design has positive timing slack:
• altering the first design to a second design to obtain substantially no positive timing slack for the first timing path by changing a location of a first transistor of the first design to a location closer to a first well boundary;
• and
• manufacturing the second design.