Biasing circuit for level shifter with isolation

A method for biasing a circuit, the method comprising:

• receiving, at an input of a timer component, an isolation (ISO) signal;
• in response to a transition of the ISO signal between a high voltage and a low voltage, injecting current for a period of time into a load circuit by a current source via control of the timer component, wherein the load circuit is coupled to a first node and wherein the high voltage is higher than the low voltage;
• outputting on the first node a biasing signal;
• generating an isolation delayed (ISO_DEL) signal, wherein the ISO_DEL signal comprises a high voltage in response to the biasing signal being within a first threshold level and wherein the ISO_DEL signal comprises a low voltage in response to the biasing signal being within a second threshold level;
• and
• outputting on a second node the ISO_DEL signal.

A biasing circuit comprising:

• a load circuit comprising a plurality of transistors, the load circuit coupled to a first node;
• a timer component, coupled to a first branch, wherein an input of the timer component is coupled to receive an isolation (ISO) signal;
• a current source configured to inject current for a period of time, as determined by the timer component, into the load circuit, via the first branch, in response to a transition of the ISO signal between a high voltage and a low voltage, wherein the high voltage is higher than the low voltage;
• and
• circuitry to generate an isolation delayed (ISO_DEL) signal,
• wherein the ISO_DEL signal comprises a high voltage in response to a biasing signal carried on the first node being within a first threshold level,
• wherein the ISO_DEL signal comprises a low voltage in response to the biasing signal being within a second threshold level, and
• wherein the biasing circuit outputs the biasing signal on the first node and outputs the ISO_DEL signal on a second node.