Logic circuit and semiconductor device including logic circuit

A logic circuit comprising:

• a first circuit;
• a first retention circuit;
• a second retention circuit;
• and
• a second circuit,
• wherein the first circuit comprises a first input node, a first output node, and a second output node,
• wherein each of the first retention circuit and the second retention circuit comprises a first transistor, a second transistor, a first capacitor, a first node, a second input node, and a third output node,
• wherein the second circuit comprises a third input node, a fourth input node, a fourth output node, and a fifth output node,
• wherein the first circuit is configured to generate first complementary data from input data of the first input node,
• wherein a piece of the first complementary data whose logic is the same as logic of the first input node is output from the first output node,
• wherein the other piece of the first complementary data is output from the second output node,
• wherein in the first retention circuit and the second retention circuit, the first capacitor is electrically connected to the first node,
• wherein in the first retention circuit and the second retention circuit, each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor,
• wherein in the first retention circuit and the second retention circuit, the first transistor is configured to control conduction between the first node and the second input node,
• wherein in the first retention circuit and the second retention circuit, the second transistor is configured to control conduction between the first node and the third output node,
• wherein in the first retention circuit and the second retention circuit, a first clock signal is input to a gate of the first transistor,
• wherein in the first retention circuit and the second retention circuit, a second clock signal is input to a gate of the second transistor,
• wherein logic of the first clock signal is opposite to logic of the second clock signal,
• wherein the second input node of the first retention circuit is electrically connected to the first output node,
• wherein the third output node of the first retention circuit is electrically connected to the third input node,
• wherein the second input node of the second retention circuit is electrically connected to the second output node,
• wherein the third output node of the second retention circuit is electrically connected to the fourth input node,
• wherein the second circuit is configured to amplify voltage between the third input node and the fourth input node and generate second complementary data,
• wherein a piece of the second complementary data is output from the fourth output node, and
• wherein the other piece of the second complementary data is output from the fifth output node.