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AssigneePyxalis
InventorGrégoire Chenebaux
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Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays.
An integrated circuit comprising N adjacent patterns, all identical, corresponding to N adjacent identical partial circuits of rank i=1 to i=N in the order of geographical succession of the partial circuits, each partial circuit comprising a main conducting line connected in cascade to the main conducting lines of the partial circuits of immediately preceding and immediately following rank, so as to allow the transmission in cascade of a master signal received on the partial circuit of rank 1, each main line introducing a propagation delay of duration T between an input of the main line and an output of the main line linked to a main line input of the circuit of immediately following rank, the integrated circuit comprising in each partial circuit of rank i:
Dependencies are inferred from the claim text.