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US 9,438,211 B1Granted
High speed latch and method
AssigneeHuawei Technologies Co., Ltd.
InventorEuhan Chong
Life of this patent
Estimating the term…
Abstract
An embodiment latch device includes a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input, and a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal. The second stage further has a reset circuit that resets a latch storage to a high value according to the clock signal.
Claims20
A latch device comprising:
- a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input;
- and
- a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal, the second stage further having a reset circuit that resets a latch storage to a high value according to the clock signal, wherein the clock signal causes the reset circuit to reset the latch storage and causes the first stage to reset in a same portion of a cycle of the clock signal.
A two stage latch circuit comprising:
- a differential stage disposed between a voltage source node and a ground node and having differential input ports, first clock input ports and clocked data signal output ports;
- and
- a regeneration stage, comprising:
- a latch storage connected at a first end to the voltage source node and having signal storage elements and output ports;
- a latch enable electrically connected between a second end of the latch storage and the ground node, the latch enable having a second clock input port;
- a clocked input control connected between the output ports and the latch enable, and having a clocked data signal input port connected to the clocked data signal output port;
- and
- a reset circuit connected to the latch storage and having third clock input ports;
- wherein a first portion of a clock signal at the first clock input ports resets the differential stage, and wherein a same first portion of the clock signal causes the reset circuit to reset the latch storage.
6 more elements
A method for storing data in a circuit, comprising:
- receiving a differential input at a differential stage;
- generating, by the differential stage, clocked data signals according to a first portion of a clock signal cycle and the differential input;
- latching values into a latch storage of a regeneration stage according to the first portion of a clock signal cycle and according to the clocked data signals;
- providing differential output signals at output ports of the latch storage according to the first portion of a clock signal cycle and according to the latched values;
- and
- resetting the latch storage to a high value according to a second portion of the clock signal cycle and resetting the differential stage at a same second portion of the clock cycle.
3 more elements
Dependencies are inferred from the claim text.