US 9,438,210 B1Granted

Semiconductor devices employing a data inversion scheme for improved input/output characteristics

AssigneeSK hynix Inc.

InventorYoung Jun Yoon

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Abstract

A semiconductor device may include a data output circuit and a control signal output circuit. The data output circuit may compare a first input signal or a second input signal with a storage datum to generate a first comparison selection signal and may compare the first input signal with the second input signal to generate a second comparison selection signal. The control signal output circuit may detect logic levels of bits included in the first and second comparison selection signals to generate first and second detection signals, generate first and second flag signals from the first and second detection signals in response to a storage flag signal, and sequentially output the first and second flag signals as transmission control signals.

Claims30

Dependent claims

A semiconductor device comprising:

a data output circuit suitable for comparing a first input signal with a storage datum to generate a first comparison selection signal and comparing a second input signal with the first input signal to generate a second comparison selection signal in a first output sequence mode that the first input signal and the second input signal are sequentially outputted as output data and suitable for comparing the second input signal with the storage datum to generate the first comparison selection signal and comparing the second input signal with the first input signal to generate the second comparison selection signal in a second output sequence mode that the second input signal and the first input signal are sequentially outputted as the output data;
and
a control signal output circuit suitable for detecting logic levels of bits included in the first and second comparison selection signals to generate a first detection signal and a second detection signal, suitable for generating a first flag signal and a second flag signal from the first and second detection signals in response to a storage flag signal, and suitable for sequentially outputting the first and second flag signals as transmission control signals.

A semiconductor device comprising:

a first pipe latch unit suitable for sequentially latching a first input signal and a second input signal in response to an input control signal and suitable for outputting the latched first and second input signals as pipe latch data in response to an output control signal;
a data storage unit suitable for storing the second input signal as a storage datum in a first output sequence mode and suitable for storing the first input signal as the storage datum in a second output sequence mode;
a data comparator suitable for comparing the first input signal with the storage datum to generate a first comparison signal, suitable for comparing the second input signal with the first input signal to generate a second comparison signal, and suitable for comparing the second input signal with the storage datum to generate a third comparison signal;
a comparison signal selector suitable for outputting the first comparison signal as the first comparison selection signal and outputting the second comparison signal as the second comparison selection signal in the first output sequence mode and suitable for outputting the third comparison signal as the first comparison selection signal and outputting the second comparison signal as the second comparison selection signal in the second output sequence mode;
and
a control signal output circuit suitable for detecting logic levels of bits included in the first and second comparison selection signals to generate a first detection signal and a second detection signal, suitable for generating a first flag signal and a second flag signal from the first and second detection signals in response to a storage flag signal, and suitable for sequentially outputting the first and second flag signals as transmission control signals.

3 more elements

A semiconductor device comprising:

a data output circuit suitable for comparing a first input signal with a storage datum to generate a first comparison selection signal and comparing a second input signal with the first input signal to generate a second comparison selection signal in a first output sequence mode that the first input signal and the second input signal are sequentially outputted as output data and suitable for comparing the second input signal with the storage datum to generate the first comparison selection signal and comparing the second input signal with the first input signal to generate the second comparison selection signal in a second output sequence mode that the second input signal and the first input signal are sequentially outputted as the output data;
a bit detector suitable for detecting logic levels of bits included in the first comparison selection signal to generate a first detection signal and suitable for detecting logic levels of bits included in the second comparison selection signal to generate a second detection signal;
a flag generator suitable for comparing the first detection signal with a storage flag signal to generate a first flag signal and suitable for comparing the first flag signal with the second detection signal to generate a second flag signal;
a flag storage unit suitable for storing the second flag signal as the storage flag signal in response to a delayed storage control signal;
a selection flag generator suitable for outputting the first flag signal as a first selection flag signal and outputting the second flag signal as a second selection flag signal in the first output sequence mode and suitable for outputting the second flag signal as the first selection flag signal and outputting the first flag signal as the second selection flag signal in the second output sequence mode;
a first pipe latch unit suitable for sequentially latching the first and second selection flag signals in response to a delayed input control signal and suitable for outputting the latched first and second selection flag signals as inversion control signals in response to a delayed output control signal;
and
a control signal output unit suitable for generating transmission control signals from the inversion control signals in synchronization with an internal clock signal,
wherein the transmission control signals are outputted through a control pad.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/808,060Filed 24 Jul 2015
Priority: KR 10-2015-004575031 Mar 2015
Granted: 6 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
G11C 7/1018
Read-write modes for single port memories, i.e. having either a random port or a serial port: serial bit line access mode, e.g. using bit line…
G11C 7/106
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output latches
G11C
Static stores

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