Implementing clock receiver with low jitter and enhanced duty cycle

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a clock receiver circuit tangibly embodied in the machine readable medium used in the design process, said clock receiver circuit for implementing low jitter and enhanced duty cycle, said clock receiver circuit comprising:
• a differential transistor pair;
• a biasing capacitor coupled to said differential transistor pair;
• an input circuit biasing a reference clock and providing biased complementary metal oxide semiconductor (CMOS) or differential clock signals to said differential transistor pair;
• multiple current mirrors coupled to said differential transistor pair for switching the polarity of input clock signals for enhanced signal performance, and
• cross coupled inverters coupled between said current mirrors for retaining clock signal symmetry, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said clock receiver circuit.