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US 9,438,208 B2Granted
Wide-band duty cycle correction circuit
AssigneeQUALCOMM Incorporated
InventorsShraddha Sridhar, Vaishnav Srinivas
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Abstract
A duty cycle correction circuit includes a rising edge variable delay circuit and a falling edge variable delay circuit. The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrected clock signal being corrected by the duty cycle correction circuit into a corrected clock signal having a desired duty cycle.
Claims21
A duty cycle correction circuit, comprising:
- a falling edge variable delay circuit for delaying a rising edge of an uncorrected clock signal into a first delayed signal;
- a first inverter for inverting the first delayed signal into an inverted first delayed signal;
- a rising edge variable delay circuit for delaying a falling edge of the uncorrected clock signal into a second delayed signal;
- a second inverter for inverting the second delayed signal into an inverted second delayed signal;
- and
- a pulse generator configured to pulse an output node voltage to a power supply voltage responsive to the first delayed signal and the first inverted delayed signal, the pulse generator being further configured to pulse the output node voltage to ground responsive to the second delayed signal and the second inverted delayed signal, wherein the pulse generator includes a first pair of switches, a second pair of switches, a third pair of switches, and a fourth pair of switches, and wherein the first pair of switches are serially connected between an output node carrying the output node voltage and a power supply node, the second pair of switches are serially connected between the output node and ground, the third pair of switches are coupled between the output node and the power supply node, and the fourth pair of switches are coupled between the output node and ground.
3 more elements
A method, comprising:
- responsive to determining that a duty cycle for an uncorrected clock signal is greater than a desired duty cycle, delaying a falling edge of the uncorrected clock signal through a falling edge variable delay circuit to produce a first delayed signal while passing the uncorrected clock signal through a rising edge variable delay circuit with no delay to produce a second delayed signal;
- responsive to determining that the duty cycle for the uncorrected clock signal is less than the desired duty cycle, delaying a rising edge of the uncorrected clock signal through the rising edge variable delay circuit to produce the second delayed signal while passing the uncorrected clock signal through the falling edge variable delay circuit with no delay to produce the first delayed signal;
- pulsing an output node voltage to a power supply voltage responsive to the first delayed signal and pulsing the output node voltage to ground responsive to the second delayed signal;
- producing a corrected clock signal having the desired duty cycle from the pulsed output node voltage;
- and
- inverting the first delayed signal to form an inverted first delayed signal, wherein pulsing the output node voltage to the power supply voltage comprises pulsing the output node voltage to the power supply voltage when the first delayed signal and the inverted first delayed signal are both grounded, wherein inverting the first delayed signal comprises processing the first delayed signal with a control signal in a logic gate.
3 more elements
A duty cycle correction circuit, comprising:
- means for variably delaying a rising edge of an uncorrected clock signal into a first delayed signal and for variably delaying a falling edge of the uncorrected clock signal into a second delayed signal;
- a pulse generator configured to pulse an output node voltage to a power supply voltage responsive to the first delayed signal, the pulse generator being further configured to pulse the output node voltage to ground responsive to the second delayed signal;
- a first inverter configured to invert the output node voltage into a corrected clock signal;
- and
- a second inverter configured to invert the first delayed signal into an inverted first delayed signal, wherein the pulse generator is further configured to pulse the output node voltage to the power supply voltage when both the first delayed signal and the inverted first delayed signal are grounded, wherein the second inverter comprises a NOR gate.
2 more elements
Dependencies are inferred from the claim text.