Dynamically programmable digital signal processing blocks for finite-impulse-response filters
AssigneeAltera Corporation
InventorVolker Mauer
Life of this patent
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Abstract
Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.
Claims25
Digital signal processing (“DSP”) block circuitry comprising:
- first switch circuitry that provides, as a first output, one of a data input and a null value;
- second switch circuitry that provides, as a second output, one of the data input, a sample cascade input, and the null value;
- third switch circuitry that selectively provides, as a third output, an add cascade input received from a first other instance of the DSP block circuitry;
- and
- combination circuitry that combines the first, second, and third outputs from the first, second, and third switch circuitries, respectively, to produce a filtered data output, wherein the combination circuitry comprises:
- first adder circuitry that adds the first output and the second output to produce a first sum;
- multiplier circuitry that multiplies the first sum with a filter coefficient input to produce a multiplication output;
- and
- second adder circuitry that adds the third output and the multiplication output to produce a second sum.
A method of configuring a programmable integrated circuit as digital signal processing (“DSP”) block circuitry, the method comprising:
- configuring logic of the programmable integrated circuit as first switch circuitry that provides, as a first output, one of a data input and a null value;
- configuring logic of the programmable integrated circuit as second switch circuitry that provides, as a second output, one of the data input, a sample cascade input, and the null value;
- configuring logic of the programmable integrated circuit as third switch circuitry that selectively provides, as a third output, an add cascade input received from a first other instance of the DSP block circuitry;
- and
- configuring logic of the programmable integrated circuit as combination circuitry that provides the first, second, and third outputs from the first, second, and third switch circuitries, respectively, to produce a filtered data output wherein the combination circuitry:
- adds the first output and the second output to produce a first sum;
- multiplies the first sum with a filter coefficient input to produce a multiplication output;
- and
- adds the third output and the multiplication output to produce a second sum.
A method of processing a signal using digital signal processing (“DSP”) block circuitry, the method comprising:
- providing, using first circuitry, as a first output, one of a data input and a null value;
- providing, using second switch circuitry, as a second output, one of the data input, a sample cascade input, and the null value;
- and
- providing, using third switch circuitry, as a third output, an add cascade input received from a first other instance of the DSP block circuitry;
- combining the first, second, and third outputs from the first, second, and third switch circuitries, respectively, to produce a filtered data output, wherein combining comprises:
- adding the first output and the second output to produce a first sum;
- multiplying the first sum with a filter coefficient input to produce a multiplication output;
- and
- adding the third output and the multiplication output to produce a second sum.
Dependencies are inferred from the claim text.