Amplification circuit adjusting duty cycle of output signal and receiver including the same
AssigneeSK hynix Inc.
InventorJae Mo Yang
Life of this patent
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Abstract
A receiver includes a first stage buffer, a second stage buffer and a third stage buffer. The first stage buffer includes an input portion electrically coupled to a first voltage node, and configured to change a voltage level of an output node in response to an input signal, first and second load portions electrically coupled between a second voltage node and the output node, and electrically coupled to each other and a duty cycle adjustment portion electrically coupled between the first and second load portions, and configured to provide a correction current to the output node through the first load portion.
Claims18
A receiver comprising:
- a first stage buffer configured to amplify an input signal;
- a second stage buffer configured to amplify an output signal of the first stage buffer;
- and
- a third stage buffer configured to amplify an output signal of the second stage buffer,
- wherein the first stage buffer includes:
- an input portion electrically coupled to a first voltage node, and configured to change a voltage level of an output node in response to the input signal;
- first and second load portions electrically coupled between a second voltage node and the output node, and electrically coupled to each other;
- and
- a duty cycle adjustment portion electrically coupled between the first and second load portions, and configured to provide a correction current to the output node through the first load portion.
A receiver comprising:
- a first stage buffer configured to amplify an input signal;
- a second stage buffer configured to amplify an output signal of the first stage buffer;
- and
- a third stage buffer configured to amplify an output signal of the second stage buffer,
- wherein the second stage buffer includes:
- an input portion electrically coupled to a first voltage node, and configured to change voltage levels of output nodes in response to the output signal of the first stage buffer;
- first and second load portions electrically coupled between a second voltage node and the output nodes, and electrically coupled to each other;
- and
- a duty cycle adjustment portion electrically coupled between the first and second load portions, and configured to provide correction currents to the output nodes through the first load portion.
A receiver comprising:
- a first stage buffer configured to amplify an input signal;
- a second stage buffer configured to amplify an output signal of the first stage buffer;
- and
- a third stage buffer configured to amplify an output signal of the second stage buffer,
- wherein the third stage buffer includes:
- a first amplifier having:
- a first input portion electrically coupled to a second voltage node, and configured to generate a first output in response to the output signal of the second stage buffer;
- a first current mirror configured to provide an amplified current to the first input portion;
- and
- first and second load portions serially coupled between a first voltage node and the first current mirror;
- a second amplifier having:
- a second input portion electrically coupled to a second voltage node, and configured to generate a second output in response to the output signal of the second stage buffer;
- a second current mirror configured to provide an amplified current to the second input portion;
- and
- third and fourth load portions serially coupled between the first voltage node and the second current mirror;
- and
- a duty cycle adjustment portion electrically coupled between the first and second load portions and the third and fourth load portions.
Dependencies are inferred from the claim text.