Digital class-D amplifier and digital signal processing method

A mobile phone platform comprising a digital class D amplifier comprising a pulse width modulator (PWM), the digital class D amplifier comprising:

• a digital loop filter having a first input configured to receive an input signal and a second input configured to receive a feedback signal, the digital loop filter configured to process, at a clock frequency, the input and feedback signals to output a filtered digital signal;
• and
• a PWM conversion module having an input for receiving the filtered digital signal and having a first output connected to the second input of the digital loop filter, the PWM conversion module configured to process the filtered digital signal and provide at the first output the feedback signal, said PWM conversion module comprising:
• a first comparator configured to compare the filtered digital signal with a first reference triangular waveform to provide a first PWM signal, the first reference triangular waveform having a frequency substantially lower than the clock frequency;
• a second comparator configured to compare the filtered digital signal with a second reference triangular waveform to provide a second PWM signal, the second reference triangular waveform being the inverse of the first triangular waveform, and the first and second PWM signals representing in their combination a differential output pulse width modulated signal;
• and
• an algebraic adder having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator, the algebraic adder configured to combine the first and said second PWM signals to provide the feedback signal.

A digital signal processing method for processing an input digital signal and obtaining an output pulse width modulated (PWM) signal, the method comprising:

• digital loop filtering, at clock frequency, the input digital signal and a feedback signal to provide a filtered digital signal;
• processing the filtered digital signal to provide the feedback signal;
• wherein processing the filtered digital signal comprises:
• comparing the filtered digital signal with a first reference triangular waveform, in a first comparator, to provide a first PWM signal, the first reference triangular waveform having a frequency substantially lower than the clock frequency;
• comparing the filtered digital signal with a second reference triangular waveform, in a second comparator, to provide a second PWM signal, the second reference triangular waveform being the inverse of the first triangular waveform;
• algebraically combining the first PWM signal and the second PWM signal to obtain the feedback signal in an algebraic adder, said algebraic adder having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator;
• wherein the output pulse width modulated signal comprises a differential signal comprising the first and second PWM signals.