Fast startup charge pump
AssigneeSmarter Microelectronics (Guang Zhou) Co., Ltd.
InventorJun Ma
Life of this patent
Estimating the term…
Abstract
A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage. During the normal working period, the pump capacitor and the output capacitor are controlled by the proper switch that is configured into the connection relationship that the charge pump can normally work in order to make the charge pump work normally. As a result of the pre-charge operation, embodiments disclosed herein can reduce the time of the output capacitor for reaching a steady state value.
Claims17
A fast startup charge pump circuit, comprising:
- a charge pump;
- and
- an output stage;
- wherein the load of the charge pump, during the period of pre-charging time, that is, during the short period of time when the charge pump starts-up, switch (Spre) and switch (Spreb) are set as:
- once the charge pump is negative charge pump, the switch (Spre) is ON (having low-impedance), the switch (Spreb) is OFF (having high-impedance);
- once the charge pump is positive charge pump, the switch (Spre) is OFF (having high-impedance), the switch (Spreb) is ON (having low-impedance);
- once the pre-charging is over, the switch (Sper) and the switch (Spreb) are in the position that opposite to the state in the period of pre-charging time.
An electronic device, comprising a fast startup charge pump circuit including:
- a charge pump;
- and
- an output stage;
- wherein a load of the charge pump is the output stage for buffering an output voltage and for reducing a voltage ripple of a current supply (IL);
- comprising an output switch (Sout), a switch (Spre) for pre-charging, a switch (Spreb), load capacitor (CL) and a current supply (IL) of the analog output load;
- wherein the output switch (Sout), load capacitor (CL) and switch (Spre) are connected in series;
- the non-capacitance (CL) connection of Spre connects to the low-voltage end of the DC voltage source;
- one terminal of the switch (Spre) is configured to be connected to a low voltage side of a DC voltage source while this terminal of the switch (Spre) is not connected to the load capacitor (CL), one terminal of the output switch (Sout) is configured to be connected to a node (Nc_n) of the last charge pump stage while this terminal of the output switch (Sout) is not connected to the load capacitor (CL), one terminal of the switch (Spreb) is connected to a common node between the switch (Spre) and the load capacitor (CL), while another terminal of the switch (Spreb) is connected to a high voltage side of the DC voltage source, one terminal of the current source IL of the analog output load is connected to a common node between the output switch (Sout) and the load capacitor (CL), while another terminal of the current source IL is connected to the low voltage side of the DC voltage source.
An electronic system comprising a plurality of fast startup charge pump circuits, each circuit comprising:
- a charge pump;
- and
- an output stage;
- wherein a load of the charge pump is the output stage for buffering an output voltage and for reducing a voltage ripple of a current supply (IL);
- comprising an output switch (Sout), a switch (Spre) for pre-charging, a switch (Spreb), load capacitor (CL) and a current supply (IL) of the analog output load;
- wherein the output switch (Sout), load capacitor (CL) and switch (Spre) are connected in series;
- the non-capacitance (CL) connection of Spre connects to the low-voltage end of the DC voltage source;
- one terminal of the switch (Spre) is configured to be connected to a low voltage side of a DC voltage source while this terminal of the switch (Spre) is not connected to the load capacitor (CL), one terminal of the output switch (Sout) is configured to be connected to a node (Nc_n) of the last charge pump stage while this terminal of the output switch (Sout) is not connected to the load capacitor (CL), one terminal of the switch (Spreb) is connected to a common node between the switch (Spre) and the load capacitor (CL), while another terminal of the switch (Spreb) is connected to a high voltage side of the DC voltage source, one terminal of the current source IL of the analog output load is connected to a common node between the output switch (Sout) and the load capacitor (CL), while another terminal of the current source IL is connected to the low voltage side of the DC voltage source.
Dependencies are inferred from the claim text.