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US 9,438,102 B2Granted
Phase locked loop having dual bandwidth and method of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorSung-Jin Kim
Life of this patent
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Abstract
A phase locked loop having a dual bandwidth is disclosed. The phase locked loop divides a loop filter into a zero filter and a pole filter, disposes the zero filter in front of a phase-frequency detector (PFD), and performs high-pass filtering on a voltage-controlled oscillator (VCO) noise with a maximum bandwidth and performs low-pass filtering on a charge pump noise (CP noise) with a minimum bandwidth to divide the VCO noise and the CP noise.
Claims15
A phase locked loop (PLL), comprising:
- a time-difference memory configured to store a first time difference between a reference input signal and a feedback signal;
- a first phase-frequency detector configured to generate a first up signal and a first down signal based on a second time difference, which is a current time difference, between the reference input signal and the feedback signal;
- a second phase-frequency detector configured to generate a second up signal and a second down signal based on the first time difference received from the time-difference memory;
- a first charge pump configured to generate a first charge current and a first discharge current in response to the first up signal and the first down signal;
- a second charge pump configured to generate a second charge current and a second discharge current in response to the second up signal and the second down signal;
- a pole filter configured to perform filtering on the first charge current, the first discharge current, the second charge current and the second discharge current to generate an oscillation control signal;
- a voltage-controlled oscillator (VCO) configured to generate an output signal having a frequency that changes in response to the oscillation control signal;
- and
- a frequency divider configured to divide the frequency of the output signal to generate the feedback signal.
6 more elements
A method of operating a phase locked loop (PLL), the method comprising:
- performing filtering using a zero filter in a time-difference domain on a reference input signal and a feedback signal to generate a first signal;
- performing filtering using a pole filter on the first signal to generate an oscillation control signal;
- and
- generating an output signal having a frequency that changes in response to the oscillation control signal.
1 more element
Dependencies are inferred from the claim text.