Apparatus and method for protecting RF and microwave integrated circuits
AssigneeAnalog Devices, Inc.
InventorsSrivatsan Parthasarathy, Rodrigo Carrillo-Ramirez
Life of this patent
Estimating the term…
Abstract
Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.
Claims18
An apparatus comprising an integrated circuit, the apparatus comprising:
- a first node configured to carry a signal;
- a second node configured to carry a voltage reference;
- a first voltage clamp of the integrated circuit, the first voltage clamp having an anode and a cathode, wherein a first parasitic capacitance associated with the anode and junction capacitance of the first voltage clamp is less than a second parasitic capacitance associated with the cathode and substrate capacitance of the first voltage clamp, wherein the anode is operatively coupled to the first node, and the cathode is operatively coupled to the second node, the first voltage clamp comprising at least a first rectifier;
- and
- a second voltage clamp of the integrated circuit, the second voltage clamp having an anode and a cathode, wherein a third parasitic capacitance associated with the cathode and junction capacitance of the second voltage clamp is less than a fourth parasitic capacitance associated with the anode and substrate capacitance of the second voltage clamp, wherein the anode is operatively coupled to the second node, and the cathode is operatively coupled to the first node, the second voltage clamp comprising at least a second rectifier.
A method of protecting a radio frequency (RF) circuit from electrostatic discharge (ESD), the method comprising:
- carrying a signal with a first node;
- carrying a voltage reference with a second node;
- clamping a voltage of the first node with a first voltage clamp of the integrated circuit, the first voltage clamp having an anode and a cathode, wherein a first parasitic capacitance associated with the anode and junction capacitance of the first voltage clamp is less than a second parasitic capacitance associated with the cathode and substrate capacitance of the first voltage clamp, wherein the anode is operatively coupled to the first node, and the cathode is operatively coupled to the second node, the first voltage clamp comprising at least a first rectifier;
- and
- clamping the voltage of the first node with a second voltage clamp of the integrated circuit, the second voltage clamp having an anode and a cathode, wherein a third parasitic capacitance associated with the cathode and junction capacitance of the second voltage clamp is less than a fourth parasitic capacitance associated with the anode and substrate capacitance of the second voltage clamp, wherein the anode is operatively coupled to the second node, and the cathode is operatively coupled to the first node, the second voltage clamp comprising at least a second rectifier.
An apparatus comprising an integrated circuit, the apparatus comprising:
- a first node configured to carry a signal;
- a second node configured to carry a voltage reference;
- a means for clamping a voltage of the first node with a first voltage clamp of the integrated circuit, the first voltage clamp having an anode and a cathode, wherein a first parasitic capacitance associated with the anode and junction capacitance of the first voltage clamp is less than a second parasitic capacitance associated with the cathode and substrate capacitance of the first voltage clamp, wherein the anode is operatively coupled to the first node, and the cathode is operatively coupled to the second node;
- and
- a means for clamping the voltage of the first node with a second voltage clamp of the integrated circuit, the second voltage clamp having an anode and a cathode, wherein a third parasitic capacitance associated with the cathode and junction capacitance of the second voltage clamp is less than a fourth parasitic capacitance associated with the anode and substrate capacitance of the second voltage clamp, wherein the anode is operatively coupled to the second node, and the cathode is operatively coupled to the first node.
Dependencies are inferred from the claim text.