Semiconductor device and method for manufacturing same
AssigneeSharp Kabushiki Kaisha
InventorYuhichi Saitoh
Life of this patent
Estimating the term…
Loading patent…
AssigneeSharp Kabushiki Kaisha
InventorYuhichi Saitoh
Estimating the term…
The present invention provides a semiconductor device which is provided with an oxide semiconductor TFT that can be reduced in the parasitic capacitance by suppressing process damage to a channel, while reducing the channel length (L). A semiconductor device of the present invention is provided with: a gate electrode (3) that is provided on a substrate (1); a first insulating layer (5) that is formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) that is formed on the first insulating layer (5); a source electrode (11) and a drain electrode (13) that are electrically connected to the oxide semiconductor layer (7); and a protective layer (9) that covers the upper surface of the oxide semiconductor layer (7). The source electrode (11) and/or the drain electrode (13) is arranged on a portion of the side faces of the oxide semiconductor layer (7) and a portion of the side faces of the protective layer (9), but does not cover the upper face of the protective layer (9).
A semiconductor device, comprising:
Dependencies are inferred from the claim text.