Field effect transistor with heterostructure channel

A field effect transistor (FET) structure, comprising:

• a heterostructure comprising:
• a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least a portion of a first source or drain region and at least a portion of a second source or drain region, respectively,
• a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
• when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section;
• and
• a gate structure configured over the channel region;
• wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate;
• wherein:
• for the p type channel region,
• the barrier section is formed of GaAs1-xSbx, and
• the first section and the section are formed of GaAs1-ySby, where 0≦x<y≦1;
• or
• for the n type channel region,
• the barrier section is formed of InxGa1-xAs, and
• the first section and the section are formed of InyGa1-yAs or GaAs1-ySby, where 0≦x<y≦1.

A method, comprising:

• providing a first layer;
• removing a first section and a second section of the first layer such that a barrier section between the first section and the second section remains;
• epitaxially growing a third section and a fourth section in place of the first section and the second section,
• a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
• when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the third section and the fourth section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the third section and the fourth section;
• and
• forming a gate structure over a portion of the third section, the barrier section, and the fourth section;
• wherein:
• providing a first layer comprises:
• forming a nanowire structure suspended over a surface of a substrate by pad regions,
• the nanowire structure comprising the first layer;
• and
• forming a sacrificial gate structure wrapping around a portion of the nanowire structure;
• removing a first section and a second section of the first layer comprises:
• removing the pad regions and the first section and the second section of the first layer;
• and
• forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
• forming a gate structure in place of the sacrificial gate structure.

A method, comprising:

• providing a first layer;
• removing a first section and a second section of the first layer such that a barrier section between the first section and the second section remains;
• epitaxially growing a third section and a fourth section in place of the first section and the second section,
• a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
• when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the third section and the fourth section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the third section and the fourth section;
• and
• forming a gate structure over a portion of the third section, the barrier section, and the fourth section;
• wherein:
• removing a first section and a second section of the first layer comprises:
• forming a hard mask over a portion of the first section, the barrier section and a portion of the second section;
• etching portions of the first layer on two sides of the hard mask;
• converting the portion of the first section, the portion of the second section into a selectively etchable material with respect to a material of the barrier section;
• and
• etching the converted portion of the first section and the portion of the section.

A semiconductor structure, comprising:

• a heterostructure comprising:
• a barrier section forming heterojunctions with a first section and a second section, respectively,
• a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
• when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section;
• a gate structure configured over a portion of the heterostructure comprising the heterojunctions,
• the gate structure comprising a dielectric layer, and a gate electrode stacked over the dielectric layer;
• and
• a first doping region and a second doping region configured in the first section and the second section on opposite sides of the gate structure, respectively,
• each of the first doping region and the second doping region having an opposite conductivity type with respect to the portion of the heterostructure over which the gate structure is configured;
• wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate.