Non-volatile semiconductor memory device

A non-volatile semiconductor memory device including one or more memory transistors each having a single layer gate structure in which a gate electrode is provided on a substrate via a gate insulating film, wherein

• the memory transistor comprises:
• a drain region formed in a surface of the substrate and connected to a bit line to which a write voltage is applied;
• a source region formed in the surface of the substrate and connected to a source line to which a write source voltage higher than the write voltage applied to the drain region via the bit line is applied;
• a carrier storage region provided on the substrate and arranged between the gate electrode and the drain region;
• a channel region formed under the gate electrode, in which current flows by applying the write source voltage higher than the write voltage applied to the drain region to the source region via the source line and applying a write gate voltage to the gate electrode via a word line;
• and
• a high resistance region formed in a region in the surface of the substrate being in contact with the drain region connected to the bit line to which the write voltage lower than the write source voltage applied to the source region is applied, facing the carrier storage region, and having a resistance value higher than a resistance value of a region between the source region and the channel region under the gate electrode;
• wherein when current flows in the channel region by applying the write gate voltage to the gate electrode while applying the write source voltage higher than the write voltage applied to the drain region to the source region, current flows in the high resistance region as well, and a strong electric field is generated in the high resistance region due to a large voltage difference with respect to the drain region, thereby accelerating carriers in the drain region to be injected into the carrier storage region.