Interface control in a bipolar junction transistor
AssigneeGlobalfoundries Inc.
InventorsKevin K. Chan, Peng Cheng, Qizhi Liu, Ljubo Radic
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Abstract
Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
Claims10
A bipolar junction transistor comprising:
- an intrinsic base layer including a raised region with a first portion and a second portion, the second portion of the raised region being thinner than the first portion of the raised region, the intrinsic base layer including a top surface, a bulk layer, and an interface layer between the bulk layer and the top surface, the interface layer comprised of silicon, the bulk layer comprised of silicon-germanium, the interface layer of the first portion of the raised region has a first thickness, and the interface layer of the second portion of the raised region has a second thickness that is less than the first thickness;
- an emitter in a contacting relationship with the interface layer of the first portion of the raised region of the intrinsic base layer at the top surface;
- and
- an extrinsic base layer in a contacting relationship with the interface layer of the second portion of the raised region of the intrinsic base layer at the top surface,
- wherein the emitter and the first portion of the raised region of the raised region of the intrinsic base layer are vertically arranged, and a p-n junction is located at an interface between the interface layer of the intrinsic base layer and the emitter.
A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a bipolar junction transistor, the HDL design structure comprising:
- an intrinsic base layer including a raised region with a first portion and a second portion, the second portion of the raised region being thinner than the first portion of the raised region, the intrinsic base layer including a top surface, a bulk layer, and an interface layer between the bulk layer and the top surface, the interface layer comprised of silicon, and the bulk layer comprised of silicon-germanium, the interface layer of the first portion of the raised region has a first thickness, and the interface layer of the second portion of the raised region has a second thickness that is less than the first thickness;
- an emitter in a contacting relationship with the interface layer of the first portion of the raised region of the intrinsic base layer at the top surface;
- and
- an extrinsic base layer in a contacting relationship with the interface layer of the second portion of the raised region of the intrinsic base layer at the top surface,
- wherein the emitter and the first portion of the raised region of the raised region of the intrinsic base layer are vertically arranged, and a p-n junction is located at an interface between the interface layer of the intrinsic base layer and the emitter.
Dependencies are inferred from the claim text.