High performance self aligned contacts and method of forming same

A method comprising:

• forming a dummy gate stack over a semiconductor substrate, wherein the dummy gate stack is disposed between gate spacers;
• conformally depositing a protective liner over the semiconductor substrate and on exposed sidewalls of the gate spacers and over a top surface of the dummy gate stack;
• forming a first inter-layer dielectric (ILD) over the protective liner;
• replacing the dummy gate stack with a conductive gate stack, wherein replacing the dummy gate stack comprises:
• performing a chemical mechanical polish (CMP) process on the ILD to expose a first portion of the protective liner over the top surface of the dummy gate stack, the first portion of the protective liner being above an uppermost surface of the gate spacer;
• and
• etching the first portion of the protective liner to expose the dummy gate stack;
• patterning a contact opening in the first ILD, wherein the contact opening exposes a second portion of the protective liner over the semiconductor substrate;
• exposing an active region at a top surface of the semiconductor substrate by removing the second portion of the protective liner over the semiconductor substrate;
• and
• filling the contact opening with a conductive material.

A method comprising:

• providing a first gate stack spaced apart from a source/drain region by a gate spacer disposed on a sidewall of the first gate stack;
• conformally depositing a metal dielectric layer on a top surface of the source/drain region and a sidewall of the gate spacer;
• forming a dielectric layer over the metal dielectric layer;
• and
• forming a contact extending through the dielectric layer and electrically connected to the source/drain region, wherein forming the contact comprises:
• patterning the dielectric layer to expose the metal dielectric layer;
• and
• etching an exposed portion of the metal dielectric layer to expose the source/drain region and a portion of the sidewall of the gate spacer.