Transistor with a low-k sidewall spacer and method of making same

A process, comprising:

• defining a gate stack on top of a semiconductor layer, said gate stack including a gate dielectric and a gate electrode;
• depositing a layer of a first dielectric material having a first dielectric constant on side walls of the gate stack to form sacrificial sidewall spacers;
• epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers;
• removing the sacrificial sidewall spacers to produce openings between each raised source-drain region and the gate stack;
• and
• depositing a layer of a second dielectric material having a second dielectric constant less than the first dielectric constant in said openings and on side walls of the gate stack to form low-k sidewall spacers, wherein the second dielectric material is selected from the group consisting of:
• silicon oxycarbonitride (SiOCN), silicon carbon oxide (SiCO), silicon carbon nitride (SiCN) and silicon boron carbon nitride (SiBCN).

A process, comprising:

• forming a gate stack on top of a semiconductor layer, said gate stack including a gate dielectric and a gate electrode;
• forming a sacrificial sidewall spacer on each side of the gate stack;
• epitaxially growing raised source-drain regions on each side of the gate stack adjacent the sacrificial sidewall spacers;
• removing the sacrificial sidewall spacers to produce openings between each raised source-drain region and the gate stack;
• and
• filling the openings with a dielectric material selected from the group consisting of:
• a silicon oxycarbonitride (SiOCN) material, a silicon carbon oxide (SiCO) material, a silicon carbon nitride (SiCN) and a silicon boron carbon nitride (SiBCN) material.