US 9,437,683 B2 · Method and structure for FinFET device

Abstract

The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

Claims20

Dependent claims

A fin-like field-effect transistor (FinFET) device comprising:

a substrate having a fin-like field-effect transistor (FET) region;
first source/drain (S/D) regions, separated by a first gate region in the FET region;
a first high-k/metal gate (HK/MG) in the first gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial silicon (Si) layer as its upper portion;
an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion;
and
the substrate as its bottom portion;
and
a first S/D feature on top of the first fin structure, having a recessed Si layer, in the first S/D region, the first S/D feature including:
a Si:C layer as its lower portion;
and a Si:P layer as its upper portion.

8 more elements

A fin-like field-effect transistor (FinFET) device comprising:

a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region;
first source/drain (S/D) regions, separated by a first gate region in the NFET region;
second source/drain (S/D) regions, separated by a second gate region in the NFET region;
a first high-k/metal gate (HK/MG) in the first gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial silicon (Si) layer as its upper portion;
an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion;
and
the substrate as its bottom portion;
a second HK/MG in the second gate region, including wrapping over an upper portion of a second fin structure, the second fin structure including:
an epitaxial SiGe layer as its upper portion;
an epitaxial Si layer as it upper middle portion;
an epitaxial SiGe layer as its lower middle portion;
and
the substrate as its bottom portion;
a first S/D feature on top of the first fin structure, having a recessed Si layer, in the first S/D region, the first S/D feature including:
a Si:C layer as its lower portion;
and
a Si:P layer as its upper portion;
and
a SiGeB S/D features on top of the second fin structure, having a recessed SiGe layer, in the second S/D region.

17 more elements

Dependencies are inferred from the claim text.

Method and structure for FinFET device

Life of this patent

Method and structure for FinFET device

Life of this patent

Abstract

Claims20