Dual channel FinFET CMOS device with common strain-relaxed buffer and method for manufacturing thereof
AssigneesImec Vzw, Samsung Electronics Co., Ltd.
InventorsSeung Hun Lee, Geert Eneman
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Abstract
A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.
Claims19
A CMOS device comprising
- a semiconductor substrate,
- a patterned strain-relaxed buffer layer of fins comprising silicon germanium (SiGe) on the semiconductor substrate;
- on the patterned strain-relaxed buffer layer, an nFinFET having an n-channel region and a pFinFET having a p-channel region, both channel regions isolated from each other by an isolation region and comprising germanium (Ge) whereby the concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer;
- source/drain regions comprising SiGe for the nFinFET;
- and
- source/drain regions comprising Ge for the pFiNFET.
A method for manufacturing a CMOS device comprising:
- providing a semiconductor substrate;
- providing a patterned strain-relaxed buffer layer of fins comprising silicon germanium (SiGe) on the semiconductor substrate;
- providing on the fins of the patterned strain-relaxed buffer layer an nFinFET and a pFinFET isolated by an isolation region, the nFinFET having an n-channel region and the pFinFET having a p-channel region, whereby both channel regions comprise germanium (Ge) in a concentration higher than the concentration of Ge in the strain-relaxed buffer layer;
- providing source/drain regions comprising SiGe for the nFinFET;
- and
- providing source/drain regions comprising Ge for the pFinFET.
Dependencies are inferred from the claim text.