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US 9,437,675 B1Granted
eDRAM for planar III-V semiconductor devices
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
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Abstract
Electronic devices including eDRAM structures are formed with a semi-insulating III-V semiconductor layer that suppresses parasitic leakage between the eDRAM transistor and the buried plate of an operatively associated trench capacitor. A low bandgap III-V semiconductor layer is used to form the buried plate.
Claims20
A method comprising:
- obtaining a structure including:
- a substrate,
- a first III-V semiconductor layer on the substrate, the first III-V semiconductor layer including a low bandgap layer, and
- a semi-insulating III-V semiconductor layer on the first III-V semiconductor layer;
- forming a plurality of first field effect transistors on a first region of the semi-insulating III-V semiconductor layer, each of the first field effect transistors including a channel region containing III-V material;
- forming a plurality of second field effect transistors on a second region of the semi-insulating III-V semiconductor layer, and
- forming a plurality of trench capacitors extending through the second region of the semi-insulating III-V semiconductor layer and within the low bandgap layer of the first III-V semiconductor layer such that each of the trench capacitors is in electrical communication with at least one of the second field effect transistors.
4 more elements
An eDRAM structure comprising:
- a substrate;
- a first III-V semiconductor layer on the substrate, the first III-V semiconductor layer including a low bandgap layer;
- a semi-insulating III-V semiconductor layer on the first III-V semiconductor layer;
- a plurality of first field effect transistors on a first region of the semi-insulating III-V semiconductor layer, each of the first field effect transistors including a channel region containing III-V material;
- a plurality of second field effect transistors on a second region of the semi-insulating III-V semiconductor layer, and
- a plurality of trench capacitors extending through the second region of the semi-insulating III-V semiconductor layer and within the low bandgap layer of the first III-V semiconductor layer, each of the trench capacitors including a buried plate comprised of the low bandgap layer of the first III-V semiconductor layer, a capacitor electrode, and a dielectric layer between the buried plate and capacitor electrode, each of the capacitor electrodes being in electrical communication with at least one of the second field effect transistors, the semi-insulating III-V semiconductor layer being operable to suppress parasitic leakage between each of the second field effect transistors and each of the buried plate.
3 more elements
An eDRAM structure comprising:
- a substrate;
- a first III-V semiconductor layer on the substrate, the first III-V semiconductor layer including a low bandgap layer;
- a semi-insulating III-V semiconductor layer on the first III-V semiconductor layer;
- an eDRAM structure including a trench capacitor extending through the semi-insulating III-V semiconductor layer and within the low bandgap layer of the first III-V semiconductor layer and a field effect transistor on the semi-insulating III-V semiconductor layer, the trench capacitor including a buried plate comprised of the low bandgap layer of the first III-V semiconductor layer, a capacitor electrode, and a dielectric layer between the buried plate and capacitor electrode, the capacitor electrode being in electrical communication with the field effect transistor, the semi-insulating III-V semiconductor layer being operable to suppress parasitic leakage between the field effect transistor and the buried plate, and
- an electrically conductive contact extending through the semi-insulating III-V semiconductor layer and electrically communicating with the buried plate.
2 more elements
Dependencies are inferred from the claim text.