Solid state devices having fine pitch structures
AssigneeHGST, Inc.
InventorDaniel R. Shepard
Life of this patent
Estimating the term…
Abstract
In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.
Claims20
A method for forming an array, the method comprising:
- forming a plurality of rows of hardmask material above one or more layers of insulating material;
- forming a plurality of columns of hardmask material above the plurality of rows of hardmask material;
- etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material;
- and
- forming memory cells in the holes,
- wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step,
- wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows;
- and
- wherein the first subset of the plurality of rows are separated by a distance corresponding to at least double a distance between array bitlines.
An electronic circuit in the form of an array comprising features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows:
- wherein the first subset of the plurality of rows are separated by a distance corresponding to double a distance between array bitlines.
An electronic system comprising one or more array circuits, the array circuits comprising features that have been formed by forming a plurality of rows of hardmask material above one or more layers of insulating material, forming a plurality of columns of hardmask material above the plurality of rows of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes, wherein a first subset of the plurality of rows are formed by a lithographic step and wherein a second subset of the plurality of rows are thereafter formed by a deposition step, and wherein the second subset of the plurality of rows are deposited between the first subset of the plurality of rows;
- wherein the first subset of the plurality of rows are separated by a distance corresponding to double a distance between array bitlines.
Dependencies are inferred from the claim text.