CMOS compatible thermopile with low impedance contact

An integrated circuit, comprising:

• a substrate comprising silicon-based semiconductor material having a top surface;
• field oxide in isolation trenches in the substrate, the field oxide providing lateral isolation between active areas of the integrated circuit;
• an area for complementary metal oxide semiconductor (CMOS) transistors comprising:
• an n-channel metal oxide semiconductor (NMOS) transistor;
• a p-channel metal oxide semiconductor (PMOS) transistor;
• and
• a plurality of contacts on source and drain regions of the NMOS transistor and the PMOS transistor, the contacts having lateral aspect ratios of 1:1 to 1.5:1 at the top surface of the substrate;
• and
• an embedded thermoelectric device comprising:
• n-type thermoelectric elements in a plurality of the active areas, the n-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
• p-type thermoelectric elements in a plurality of the active areas, the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
• a plurality of stretch contacts on the n-type thermoelectric elements and the p-type thermoelectric elements, the stretch contacts having lateral aspect ratios greater than 4:1 at the top surface of the substrate, wherein the stretch contacts and the contacts have a common layer structure;
• and
• a plurality of interconnects of metal levels and vias of via levels of the integrated circuit connecting the stretch contacts to a thermal node.