3D NAND array architecture

A memory device on a substrate, comprising:

• a multilevel stack of conductive layers, each of the layers being divided laterally into a set of at least one word line;
• a plurality of pillars oriented orthogonally to the conductive layers, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers;
• a plurality of string select lines disposed above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective string select gate of the pillar, a number NSSL of the string select lines superposing a first one of the word lines;
• a plurality of parallel bit line conductors disposed above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, the bit line conductors in the plurality having a pitch pBL, each of the pillars underlying one of the bit line conductors, none of the bit line conductors in the plurality of bit line conductors intersecting more than one of the pillars which underlie a single one of the string select lines;
• and
• a plurality of ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, a number NGSL of the ground select lines underlying the first word line,
• wherein the pillars in the plurality of pillars are arranged on a regular grid having two lateral dimensions, the regular grid having a unit cell of four of the pillars A, B, C and D located at vertices of a parallelogram, and all intersecting a single one of the ground select lines,
• pillar B being a pillar which is nearest to pillar A in the grid,
• and pillar C being a pillar which is non-collinear with pillars A and B but which is otherwise nearest pillar A in the grid,
• wherein two adjacent ones of the ground select lines which underlie one of the conductive layers have respective widths in the bit line direction which are at least as large as (α/pBL), α being the area of the unit cell.