Temperature compensation method for high-density floating-gate memory

A non-volatile memory arrangement, comprising:

• a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor;
• a first current reference circuit and a second current reference circuit, the first and second current reference circuit each having a floating gate transistor operating in a weak-inversion mode and a varactor having a first terminal electrically coupled to a gate node of the floating gate transistor;
• and
• a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes.

A non-volatile memory arrangement, comprising:

• a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with a first terminal electrically coupled to the gate node of the floating gate transistor;
• a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;
• a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;
• and
• a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage that maintains the ratio between the reference currents constant and applies the tuning voltage to a second terminal of the varactor in the first memory circuit.

A non-volatile memory arrangement comprising:

• an array of memory circuits, each memory circuit having a floating gate transistor operating in weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;
• a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;
• a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor;
• and
• a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage in accordance with the ratio between the reference currents and applies the tuning voltage to the varactor of each memory circuit in the array of memory circuits.