Electrostatic discharge protection device and electrostatic discharge protection system

An electrostatic discharge protection device disposed on a substrate, comprising:

• a first MOS transistor structure, comprising:
• a first well, having a first conductive type and disposed on the substrate;
• a second well, having a second conductive type and disposed on the substrate, wherein the second well is adjacent to the first well, and the second conductive type is different from the first conductive type;
• and
• a first doping region, having a second conductive type and disposed in the first well;
• a second MOS transistor structure, comprising:
• the first well;
• the second well;
• and
• a second doping region, having a first conductive type and disposed in the second well;
• a first poly-silicon region, disposed on the first well;
• a second poly-silicon region, disposed on the second well;
• and
• a first protection layer, disposed between the first poly-silicon region and the second poly-silicon region, wherein the first protection layer covers a portion of the first well, a portion of the second well, a portion of the first poly-silicon region and a portion of the second poly-silicon region, and there is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.

An electrostatic discharge protection system, comprising:

• an electrostatic discharge protection device, coupled between a first voltage pad, a second voltage pad and an IO pad, wherein the electrostatic discharge protection comprises:
• a substrate;
• a first well, having a first conductive type and disposed on the substrate;
• a second well, having a second conductive type and being disposed on the substrate, wherein the second well is adjacent to the first well, and the second conductive type is different from the first conductive type;
• a first poly-silicon region, disposed on the first well, wherein a first node connects to the first well through the first poly-silicon region;
• a second poly-silicon region, disposed on the second well, wherein a second node connects to the second well through the second poly-silicon region;
• and
• a first protection layer, disposed between the first poly-silicon region and the second poly-silicon region, wherein the first protection layer covers a portion of the first well, a portion of the second well, a portion of the first poly-silicon region and a portion of the second poly-silicon region, and there is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.