Semiconductor package and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorMin Gi Hong
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor package in which a cell array region and a peripheral circuit region are formed as different semiconductor chips, respectively. First semiconductor chips including memory cells and a second semiconductor chip including only peripheral circuitry common to the first semiconductor chips are electrically connected to each other. Thus, a loading capacitance of the semiconductor package may be reduced. As a result, an RC delay of the semiconductor package may be reduced, thereby improving an operating speed of the semiconductor package.
Claims11
A semiconductor package comprising:
- a package substrate including a top surface, a bottom surface, and an opening;
- a first semiconductor chip at a central region of the package substrate, the first semiconductor chip including peripheral circuits in a peripheral circuit region;
- and
- a plurality of second semiconductor chips on a first region and a second region of the package substrate, the opening disposed between the first region and the second region of the package substrate, each of the plurality of second semiconductor chips including a cell array region in which memory cells are disposed,
- wherein the peripheral circuits in the first semiconductor chip are configured to drive the memory cells in the second semiconductor chips,
- wherein the first semiconductor chip partially overlaps with the opening and does not entirely cover the opening.
A semiconductor package comprising:
- a package substrate;
- a plurality of first semiconductor chips each including memory cells;
- and
- a second semiconductor chip including peripheral circuitry common to the first semiconductor chips, the peripheral circuitry configured to drive together the memory cells in two or more of the first semiconductor chips, wherein
- each of the first semiconductor chips does not include a peripheral circuitry configured to drive the memory cell and the second semiconductor chip does not include a memory cell,
- the package substrate includes a top surface, a bottom surface, and an opening defined at a location,
- the first semiconductor chips are on the top surface,
- the second semiconductor chip is on the bottom surface and overlaps with the opening, and
- the second semiconductor chip does not entirely cover the opening.
A semiconductor package comprising:
- a package substrate including a bottom surface, a top surface, and a hole;
- a peripheral circuit chip at a central region of the bottom surface of the package substrate, wherein the peripheral circuit chip overlaps the hole;
- and
- a plurality of memory chips including first to Nth memory chips on the top surface of the package substrate at both sides of the peripheral circuit chip,
- wherein a second memory chip is stacked on the first memory chip by partially overlapping the first memory chip,
- wherein the Nth memory chip is stacked on a N-1th memory chip by partially overlapping the N-1th memory chip,
- wherein the Nth memory chip does not overlap with the hole, and
- where “N” denotes a natural number of 2 or more.
Dependencies are inferred from the claim text.